Let’s also assume that the setup and hold times of the flops are zero for this example. Let’s take the clock period of the circuit as 10ns, with 2ns insertion to delay to clock pin of each register. Given below is a design with zero skew, but setup timing violation. Let us first see an example of clock being skewed to meet timing. P&R tools can use useful skew as an optimization option in CTS and other stage optimizations to leverage the clock signal in meeting timing, with acceptable margins. If clock skew is used intentionally to meet timing then it is called useful skew. ![]() ![]() However, meeting zero skew in some large designs can be unnecessarily costly. You are ensuring the clock signals come to each data sync point within a permissible variation, and the design can theoretically be timing closed if the data paths also can meet the timing within a permissible range of the clock signal. Here, your clock design is completely independent of your data path design. ![]() For each of the sinks, the insertion delay is kept to be equal so that each node receives the clock at the same time(or as close as physically possible). For clock trees, the traditional way is to go with zero skew or balanced skew.
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